Processors such as a baseband processor, a video processor, and a multimedia processor which are used in a portable communication terminal like a cellular phone have a static random access memory (SRAM) external interface (or pseudo SRAM (PSRAM) external interface) and a synchronous dynamic random access memory (SDRAM) external interface.
A dual port memory is usually used in processors with the SRAM external interface (or PSRAM external interface) and the SDRAM external interface.
A dual port memory has two I/O ports and accesses data through the two ports such that a first processor accesses data through a first port and a second processor accesses data through a second port.
A case of using a dual port memory is faster in data transmission rate and more excellent in system performance than a case where two processors are coupled to different memories to exchange data via an external printed circuit board (PCB) line by a host processor interface. Using a dual port memory, there is an effect of reducing one memory in terms of the mounting area size.
FIGS. 1 and 2 are schematic diagrams illustrating dual port memories used by
FIGS. 1 and 2 are schematic diagrams illustrating dual port memories used by two processors which access memories with the same kind of memory cell structure. In detail, FIG. 1 is a schematic diagram illustrating a dual port memory used by a processor A with an SDRAM external bus interface (EBI) and a processor B with an SDRAM external bus interface (EBI) according to a conventional art, and FIG. 2 is a schematic diagram illustrating a dual port memory used by a processor A with an SRAM external bus interface (EBI) and a processor B with an SRAM external bus interface (EBI) according to the conventional art. Here, the external bus interface (EBI) serves as a sort of a memory controller.
As shown in FIGS. 1 and 2, a dual port memory with two ports may be used by the two processors which access a memory with the same kind of memory cell structure. That is, in case of FIG. 1, a dual port memory in which a memory cell array includes a DRAM is coupled to the two processors with the SDRAM external bus interface (EBI). Also, in case of FIG. 2, a dual port memory in which a memory cell array includes a SRAM is coupled to the two processors with the SRAM external bus interface (EBI).
However, such a dual port memory is difficult to be used between two processors with external bus interfaces (EBI) for different kinds of memories since unit memory cell structures are different.
An SDRAM is a volatile memory and stores data by periodically performing a refresh operation to periodically fill charges into a capacitor. Such an SDRAM has a unit memory cell structure of a DRAM comprised of one transistor and one capacitor.
An SRAM is a volatile memory in which data are erased when powered off, and it can maintain data stored in a memory cell while powered on even though a refresh operation is not performed. A unit memory cell of an SRAM has a structure comprised of four transistors with a latch structure and two transistors with a transmission gate structure, i.e., total six transistors. Since data are stored in a unit memory cell of a latch structure, a refresh operation for preserving data is not required. A unit memory cell of an SRAM is realized by six transistors, and so it has a disadvantage in the layout area size, compared to a unit memory cell of a DRAM comprised of one transistor and one capacitor.
A PSRAM uses the same interface as an SRAM, but it has a unit memory cell structure of a DRAM comprised of one transistor and one capacitor and has a refresh circuit built therein.
It is difficult to form both an SRAM memory cell and a DRAM memory cell which have different memory cell structures on a memory cell array region of a dual port memory due to restrictions in a semiconductor memory manufacturing process.
That is, in case where a processor A has an SRAM external bus interface (EBI) and a processor B has an SDRAM external bus interface (EBI), it is difficult to manufacture a dual port memory in which both an SRAM memory cell and a DRAM memory cell are formed on a memory cell array region due to restrictions in a semiconductor memory manufacturing process.
When both an SRAM memory cell and a DRAM memory cell are formed on a memory cell array region of a dual port memory, a manufacturing cost is increased because the size of a die is increased due to an SRAM memory cell comprised of six transistors.
For these reasons, a memory cell array of a conventional dual port memory is realized by one kind of memory cell structure of either an SRAM or a DRAM. In this instance, using a DRAM as a memory cell array of a dual port memory is more efficient in layout area size than using an SRAM.
A portable communication terminal gradually demands more processors, and to this end, a dual port memory is required which can be used between processors which have different memory interfaces.
Particularly, in a portable communication terminal like a cellular phone, required is a dual port memory with a DRAM memory cell structure which can be used by a processor with an SRAM external interface (or PSRAM external interface) and a processor with an SDRAM external interface.
A conventional dual port memory has a fixed memory interface logic so that a first port is used for data access from a processor with an SDRAM external interface and a second port is used for data access from either a processor with an SDRAM external interface or a processor with a PSRAM external interface.
Therefore, in the conventional dual port memory in which the first port is coupled to the processor with the SDRAM external interface and the second port is coupled to the processor the SDRAM external interface, the second port can not be coupled to a processor with a PSRAM (or SRAM) external interface.
That is, the conventional dual port memory has a disadvantage in that it can not be coupled to either a processor with an SDRAM external interface or a processor with a PSRAM (or SRAM) external interface according to its need.
For this reason, the conventional dual port memory can not satisfy demand of a portable communication terminal which requires gradually more processors because there is a restriction to accessible processors.